4-BIT SINGLE-CHIP MICROCOMPUTER

MOS INTEGRATED CIRCUIT

Document No. IC-3189

The mark 5

shows the major revised points.

(O.D. No. IC-8696)
Date Published January 1994P
Printed in Japan

PD75P316B

DESCRIPTION

The

PD75P316B is a product of the

PD75316B with its built-in ROM having been replaced with the one-

time PROM.

It is most suitable for test production during system development and for production in small amounts since

it can operate under the same supply voltage as mask products.

The one-time PROM product is capable of writing only once and is effective for production of many kinds of

sets in small quantities and early startup.

The EPROM product allows programs to be written and rewritten, making it ideal for system evaluation.

Functions are described in detail in the following User'S Manual, which should be read when carrying out

design work.

PD75308 User's Manual: IEM-5016

FEATURES

Compatible (excluding mask option) with the

PD75312B/75316B (mask products)

Memory capacity

· Program memory (PROM) : 16256

8 bits

· Data memory (RAM)

: 1024

4 bits

· Ideal for small set as camera, etc.

DATA SHEET

ORDERING INFORMATION

Ordering Code

Package

Internal ROM

Quality Grade

PD75P316BGC-3B9

80-pin plastic QFP (

14 mm)

One-time PROM

Standard

PD75P316BGK-BE9

80-pin plastic QFP (fine pitch) (

12 mm)

One-time PROM

Standard

PD75P316BKK-T*

80-pin ceramic WQNF (LCC with window)

EPROM

Not applicable

(for function evaluation)

Under Development

Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

The information in this document is subject to change without notice.

The

PD75P316B EPROM product does not provide a level of reliability suitable for use as a

volume production product for customers' devices. The EPROM product should be used solely for

function evaluation in experiments or preproduction.

In descriptions common to one-time PROM products and EPROM products in this document, the term

"PROM" is used.

PD75P316B

PIN CONFIGURATION (Top View)

· 80-pin plastic QFP (

14 mm)

· 80-pin plastic TQFP (fine pitch)(

12 mm)

· 80-pin ceramic WQFN (LCC with window)

In normal operation, V

input should be the V

level.

P00-03

: Port 0

LC0-2

: LCD Power Supply 0-2

P10-13

: Port 1

BIAS

: LCD Power Supply Bias Control

P20-23

: Port 2

LCDCL

: LCD Clock

P30-33

: Port 3

SYNC

: LCD Synchronization

P40-43

: Port 4

TI0

: Timer Input 0

P50-53

: Port 5

PTO0

: Programmable Timer Output 0

P60-63

: Port 6

BUZ

: Buzzer Clock

P70-73

: Port 7

PCL

: Programmable Clock

BP0-7

: Bit Port

INT0, 1, 4

: External Vectored Interrupt 0, 1, 4

KR0-7

: Key Return

INT2

: External Test Input 2

SCK

: Serial Clock

X1, 2

: Main System Clock Oscillation 1, 2

: Serial Input

XT1, 2

: Subsystem Clock Oscillation 1, 2

: Serial Output

MD0-3

: Mode Selection

SB0, 1

: Serial Bus 0, 1

: Positive Power Supply

RESET

: Reset Input

: Ground

S0-31

: Segment Output 0-31

: Programing/Verifying Power

COM0-3 : Common Output 0-3

S31/BP7

8079787776 757473 7271 70696867666564636261

60
59

2122232425 262728 2930 31323334353637383940

S19

S23

S22

S21

P60/KR0

P33/MD3

P32/MD2

P31/SYNC/MD1

P30/LCDCL/MD0

P23/BUZ

P22/PCL

P21

P20/PTO0

P13/TI0

P12/INT2

P11/INT1

P10/INT0

P03/SI/SB1

COM0

COM1

COM2

COM3

BIAS

LC0

LC1

LC2

P40

P41

P42

P43

P50

P51

P52

P53

P00/INT4

P01/SCK

P02/SO/SB0

S11

S10

RESET

P73/KR7

P72/KR6

P71/KR5

P70/KR4

P63/KR3

P62/KR2

P61/KR1

XT2

XT1

S30/BP6

S29/BP5

S28/BP4

S27/BP3

S26/BP2

S25/BP1

S24/BP0

S20

S18

S17

S16

S15

S14

S13

S12

PD75P316BGC-3B9

PD75P316BGK-BE9

PD75P316BKK-T

PD75P316B

BLOCK DIAGRAM

PROGRAM

COUNTER (14)

PROGRAM

MEMORY

(PROM)

16256

8 BITS

LCD

CONTROL-

LER

/DRIVER

S0-S23

S24/BP0
S31/BP7

COM0COM3

LC0

LC2

BIAS
LCDCL/P30
SYNC/P31

GENERAL REG.

DATA

MEMORY

(RAM)

1024

4 BITS

BANK

SP(8)

ALU

DECODE

AND

CONTROL

BIT SEQ.

BUFFER (16)

P00-P03

P10-P13

P20-P23

P30-P33
/MD0-MD3

PORT4

P40-P43

PORT5

P50-P53

PORT6

P60-P63

PORT7

P70-P73

PORT3

PORT2

PORT1

PORT0

LCD

RESET

CPU
CLOCK

STAND BY
CONTROL

SYSTEM CLOCK

GENERATOR

SUB

MAIN

CLOCK

DIVIDER

CLOCK

OUTPUT

CONTROL

XT2

XT1

PCL/P22

/ 2

BASIC

INTERVAL

TIMER

INTBT

TIMER/EVENT

COUNTER

INTT0

TI0/P13

PTO0/P20

WATCH

TIMER

INTW

LCD

BUZ/P23

SERIAL BUS

INTERFACE

INTCSI

SCK/P01

SO/SB0/P02

SI/SB1/P03

INTERRUPT

CONTROL

KR0/P60

KR7/P73

INT4/P00

INT2/P12

INT1/P11

INT0/P10

PD75P316B

CONTENTS

PIN FUNCTIONS .........................................................................................................................................

1.1

PORT PINS ........................................................................................................................................................... 5

1.2

OTHER PINS ......................................................................................................................................................... 7

1.3

PIN INPUT/OUTPUT CIRCUITS ......................................................................................................................... 9

DIFFERENCES BETWEEN PRODUCTS IN SERIES ................................................................................

DATA MEMORY (RAM) ............................................................................................................................

PROGRAM MEMORY WRITE AND VERIFY ............................................................................................

4.1

PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ....................................................................... 14

4.2

PROGRAM MEMORY WRITING PROCEDURE ............................................................................................... 15

4.3

PROGRAM MEMORY READING PROCEDURE ............................................................................................... 16

4.4

ERASURE PROCEDURE(

PD75P316BKK-T-ONLY) ........................................................................................ 17

ELECTRICAL SPECIFICATIONS ...............................................................................................................

PACKAGE INFORMATION .......................................................................................................................

RECOMMENDED SOLDERING CONDITIONS ........................................................................................

APPENDIX A. DEVELOPMENT TOOLS .........................................................................................................

APPENDIX B. RELATED DOCUMENTS ........................................................................................................

PD75P316B

PIN FUNCTIONS

1.1

PORT PINS (1/2)

Input

Input/output

Input

Input/output

P00

P01

P02

P03

P10

P11

P12

P13

P20

P21

P22

P23

P30 *2

P31 *2

P32 *2

P33 *2

P40 to P43*2

P50 to P53 *2

P60

P61

P62

P63

P70

P71

P72

P73

Dual-Function

INT4

SCK

SO/SB0

SI/SB1

INT0

INT1

INT2

TI0

PTO0

PCL

BUZ

LCDCL MD0

SYNC

MD1

MD2

MD3

KR0

KR1

KR2

KR3

KR4

KR5

KR6

KR7

I/O Circuit

Type*1

F - A

F - B

M - C

B - C

E - B

M - A

F - A

Input

High impedance

Input

4-bit input port (PORT0)
Internal pull-up resistor specification by
software is possible for P01 to P03 as a 3-bit
unit.

4-bit input port (PORT1)
Internal pull-up resistor specification by
software is possible as a 4-bit unit.

4-bit input/output port (PORT2)
Internal pull-up resistor specification by
software is possible as a 4-bit unit.

Programmable 4-bit input/output port (PORT3)
Input/output settable bit-wise.
Internal pull-up resistor specification by
software is possible as a 4-bit unit.

N-ch open-drain 4-bit input/output port (PORT
4).
Data input/output pins for program memory
(PROM) write/verify (low-order 4 bits).

N-ch open-drain 4-bit input/output port (PORT
5)
Data input/output pins for program memory
(PROM) write/verify (high-order 4 bits).

Programmable 4-bit input/output port (PORT6).
Input/output settable bit-wise.
Internal pull-up resistor specification by
software is possible as a 4-bit unit.

4-bit input/output port (PORT7).
Internal pull-up resistor specification by
software is possible as a 4-bit unit.

With noise elimination circuit

Pin Name

Input/Output

Function

8-bit I/O

Afer Reset

Input/output

* 1.

: Indicates a Schmitt-triggered input.

2 .

Direct LED drive capability.

PD75P316B

1.2

OTHER PINS

Input

External event pulse input pin for timer/event counter.

Timer/event counter output pin

Clock output pin

Fixed frequency output pin (for buzzer or system clock
trimming)

Serial clock input/output pin

Serial data output pin
Serial bus input/output pin

Serial data input pin
Serial bus input/output pin

Edge-detected vectored interrupt input pin (rising or
falling edge detection).

Edge-detected vectored interrupt input pin (detection
edge selectable)

Edge-detected testable input pin (rising edge detection)

Testable Input/output pins (parallel falling edge detection)

Main system clock oscillation crystal/ceramic connection
pins. When an external clock is used, the clock is input
to X1 and the inverted clock to X2.

Subsystem clock oscillation crystal connection pins
When an external clock is used, the clock is input to XT1
and the inverted clock toXT2. XT1 can be used as a 1-bit
input (test) pin.

System reset input pin (low-level active).

Mode selection pin for program memory (PROM) write/
verify.

Program voltage application pin for program memory
(PROM) write/verify . Connected to V

in normal

operation. Applies +12.5 V in program memory write/
verify.

Positive power supply pin

GND potential pin

Dual-

Function Pin

P13

P20

P22

P23

P01

P02

P03

P00

P10

P11

P12

P60 to P63

P70 to P73

P30 to P33

Pin Name

Input/Output

Function

After Reset

Input

output

Input/output

Input

Input/output

Input

Input/output

I/O Circuit

Type

B - C

E - B

F - A

F - B

M - C

B - C

F - A

E - B

S0 to S23

S24 to S31

COM0 to COM3

LC0

to V

LC2

BIAS

LCDCL*2

SYNC*2

Output

Input/output

BP0 to 7

P30

P31

Segment signal output pins

Common signal output pins

LCD drive power supply pins

External split cutting output pin

External extension driver drive clock output pin

External extension driver synchronization clock output
pin

High impedance

Input

G - A

G - B

E - B

TI0

PTO0

PCL

BUZ

SCK

SO/SB0

SI/SB1

INT4

INT0

INT1

INT2

KR0 to KR3

KR4 to KR7

X1, X2

XT1, XT2

RESET

MD0 to MD3

PD75P316B

1.3

PIN INPUT/OUTPUT CIRCUITS

The input/output circuits for each of the pin

PD75P316B are shown below in partially simplified form.

P-ch

OUT

N-ch

data

output
disable

Schmitt-Trigger Input with Hysteresis Characteristic

P-ch

N-ch

P.U.R.

P-ch

IN/OUT

P.U.R.
enable

data

output
disable

Type D

Type A

P.U.R.:Pull-Up Resistor

P.U.R.

P-ch

IN/OUT

P.U.R.
enable

data

output
disable

Type D

Type B

P.U.R.:Pull-Up Resistor

CMOS Standard Input Buffer

Push-pull output that can be made high-impedance output

(P-ch and N-ch OFF)

TYPE A (For TYPE E-B)

TYPE D (For TYPE E-B, F-A)

TYPE B

TYPE E-B

TYPE F-A

TYPE B-C

P-ch

P.U.R.

P.U.R.
enable

P.U.R. : Pull-Up Resistor

PD75P316B

N-ch

P-ch

OUT

SEG
data

P-ch

LC0

LC1

LC2

N-ch

LC0

LC1

LC2

COM
data

N-ch

P-ch

N-ch

OUT

N-ch

P-ch

TYPE F-B

TYPE G-O

TYPE M-A

TYPE G-A

TYPE G-B

TYPE M-C

P.U.R.

IN/OUT

P.U.R.
enable

output

disable

(P)

output
disable

data

output

disable

(N)

P-ch

N-ch

P-ch

P.U.R.:Pull-Up Resistor

IN/OUT

N-ch
(+10 V
Withstand
Voltage)

data

output
disable

Middle-High Voltage Input Buffer
(+10 V Withstand Voltage)

N-ch

P-ch

OUT

P-ch

N-ch

LC0

LC1

LC2

SEG data/
Bit Port data

P.U.R.
enable

IN/OUT

P-ch

N-ch

data

output
disable

P.U.R.:Pull-Up Resistor

P.U.R.

PD75P316B

2. DIFFERENCES BETWEEN PRODUCTS IN SERIES

The

PD75P316B is a version of the

PD75316B with its built-in mask ROM replaced with the one-time PROM

or EPROM. When performing debugging or preproduction of an application system using PROM and then

volume production using a mask ROM product, etc., these differences should be taken into account in the

transition. Table 2-1 shows the differences from the other products in series.

For the details of the CPU functions and the built-in hardware, please refer to the

PD75308 User's Manual

(IEM-5016).

Product Name

Comparison Item

· 80-pin plastic QFP

(

14 mm)

· 80-pin plastic TQFP

(fine pitch)(

12 mm)

· 80-pin plastic QFP

(

14 mm)

· 80-pin plastic TQFP

(fine pitch)(

12 mm)

· 80-pin ceramic QWFN

(LCC with window)

Table 2-1 Differences between Products in Series

PD75P316A

PD75P316B

PD75312B/75316B

Program memory (bytes)

· EPROM/one-time PROM

· One-time PROM

· Mask ROM

· 16256

· EPROM

· 12160/16256

· 16256

Data memory (x 4 bits)

1024

Pull-up resistors of ports 4 and 5

None

Incorporation specifiable
by mask option

LCD driving power supplying split

None

Incorporation specifiable

resistor

by mask option

Pin connection

No.50 to 55

P30/MD0 to P33/MD3

P30 to P33

No.57

The mask ROM products and PROM products have different consumption

Electrical specifications

currents, etc. See the Electrical Specifications section in the relevant Data Sheets
for details.

Power supply voltage range

2.7 to 6.0 V

2.0 to 5.5 V

· 80-pin plastic QFP
(14

20 mm)

Package

· 80-pin ceramic WQNF

(LCC with window)

Other

The mask ROM products and PROM products have different circuit scales and
mask layouts, and therefore differ in terms of noise resistance and noise radiation.

Noise resistance and noise radiation differs between the PROM products and mask ROM products. When

investigating a switch from PROM product to mask PROM product in the transition from preproduction to

volume production, thorough evaluation should be carried out with the mask ROM CS product (not the ES

product).

PD75P316B

DATA MEMORY (RAM)

Fig. 3-1 shows the data memory configuration. It consists of a data area and a peripheral hardware area.

The data area consists of memory banks 0 to 3 with each bank consisting of 256 words x 4 bits.

Peripheral hardware has been assigned to the area of memory bank 15.

(1)

Data area

The data area comprises a static RAM. It is used to store program data and as a subroutine, interrupt

execution stack memory. Even if the CPU operation is stopped in the standby mode, it is possible to hold the

memory content for a long time by battery backup, etc. The data area is operated by memory manipulation

instructions.

The static RAM has been mapped to memory banks 0, 1, 2 and 3 by 256 x 4 bits each. Bank 0 has been

mapped as a data area but is also available as a general register area (000H to 007H) and a stack area (000H

to 0FFH) (banks 1, 2 and 3 are available only as a data area).

In the static RAM, 1 address consists of 4 bits. It can be operated in units of 8 bits by 8-bit memory ma-

nipulation instructions or in bits by bit manipulation instructions, however. In an 8-bit manipulation instruc-

tion, an even address should be specified.

(a)

General register area

The general register area can be operated either by general register operation instructions or by memory

manipulation instructions. Up to eight 4-bit registers are available. That part of the 8 general registers

which is not used in the program is available as a data area or a stack area.

(b) Stack area

The stack area is set by an instruction. It is available as a subroutine execution or interrupt service

execution save area.

(2)

Peripheral hardware area

The peripheral hardware area has been mapped to F80H to FFFH of memory bank 15.

It is operated by memory manipulation instructions just as the static RAM. In the peripheral hardware,

however, the operable bit unit differs from one address to another. An address to which peripheral hardware

has not been assigned is inaccessible since no data memory is built in.

PD75P316B

PROGRAM MEMORY WRITE AND VERIFY

The ROM built into the

PD75P316B is a 16256 x 8-bit electrically writable one-time PROM. The table below

shows the pins used to program this PROM. There is no address input; instead, a method to update the ad-

dress by the clock input via the X1 pin is adopted.

Function

Voltage applecation pin for program memory write/verify

(normally V

potential).

Address update clock inputs for program memory write/

verify. Inverse of X1 pin signal is input to X2 pin.

Operating mode selection pin for program memory write/

verify.

8-bit data input/output pins for progrm memory write/

verify.

Supply voltage application pin.

Applies 2.0 to 5.5 V in normal operation, and 6 V for

program memory write/verify.

Pin Name

X1, X2

MD0 to MD3

P40 to P43 (low-order 4 bits)

P50 to P53 (high-order 4 bits)

4.1

PROGRAM MEMORY WRITE/VERIFY OPERATING MODES

The

PD75P316B assumes the program memory write/verify mode when +6 V and +12.5 V are applied

respectively to the V

and V

pins. The table below shows the operating modes available by the MD0 to MD3

pin setting in this mode. All the remaining pins are at the V

potential by the pull-down resistor.

+12.5 V

+6 V

MD0

MD1

MD2

MD3

Operating Mode

Program memory address zero-clear

Write mode

Verify mode

Program inhibit mode

Operating Mode Setting

X: L or H

PD75P316B

4.2

PROGRAM MEMORY WRITING PROCEDURE

The program memory writing procedure is shown below. High-speed write is possible.

(1)

Pull down a pin which is not used to V

via the resistor. The X1 pin is at the low level.

(2)

Supply 5 V to the V

and V

pins.

(3)

s wait.

(4)

The program memory address 0 clear mode.

(5)

Supply 6 V and 12.5 V respectively to V

and V

(6)

The program inhibit mode.

(7)

Write data in the 1-ms write mode.

(8)

The program inhibit mode.

(9)

The verify mode. If written, proceed to (10); if not written, repeat (7) to (9).

(10) (Number of times written in (7) to (9): X) x 1-ms additional write.

(11) The program inhibit mode.

(12) Update (+1) the program memory address by inputting 4 pulses to the X1 pin.

(13) Repeat (7) to (12) up to the last address.

(14) The program memory address 0 clear mode.

(15) Change the V

and V

pins voltage to 5 V.

(16) Power off.

The diagram below shows the procedure of the above (2) to (12).

Data Input

Write

Verify

Additional
Write

Address
Increment

Repeated X Times

Data Output

+ 1

P40-P43
P50-P53

MD0
(P30)

MD1
(P31)

MD2
(P32)

MD3
(P33)

PD75P316B

4.3

PROGRAM MEMORY READING PROCEDURE

The

PD75P316B can read the content of the program memory in the following procedure. It reads in the

verify mode.

(1)

Pull down a pin which is not used to V

via the resistor. The X1 pin is at the low level.

(2)

Supply 5 V to the V

and V

pins.

(3)

s wait.

(4)

The program memory address 0 clear mode.

(5)

Supply 6 V and 12.5 V respectively to V

and V

(6)

The program inhibit mode.

(7)

The verify mode. If clock pulses are input to the X1 pin, data is output sequentially 1 address at a time at

the period of inputting 4 pulses.

(8)

The program inhibit mode.

(9)

The program memory address 0 clear mode.

(10) Change the V

and V

pins voltage to 5 V.

(11) Power off.

The diagram below shows the procedure of the above (2) to (9).

Data Output

P40-P43
P50-P53

MD0
(P30)

MD1
(P31)

MD2
(P32)

MD3
(P33)

"L"

+ 1

PD75P316B

4.4

ERASURE PROCEDURE (

PD75P316BKK-T ONLY)

The data programmed in the

PD75P316B can be erased by exposure to ultraviolet radiation through the

window in the top of the package.

Erasure is possible using ultraviolet light with a wavelength of approximately 250 nm. The exposure re-

quired for complete erasure is 15 W.s/cm

(UV intensity x erasure time).

Erasure takes aproximately 15 to 20 minutes using a commercially available UV lamp (254 nm wavelength,

12 mW/cm

intensity).

Note 1.

Program contents may also be erased by extended exposure to direct sunlight or fluorescent light.

The contents should therefore be protected by masking the window in the top of the package with

light-shielding film.

The light-shielding film provided with NEC's UV EPROM products should be used.

Erasure should normally be carried out at a distance of 2.5 cm or less from the UV lamp.

Remarks

The erasure time may be increased due to deterioration of the UV lamp or dirt on the package

window.

PD75P316B

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (Ta = 25

The r.m.s. value should be calculated as follows [R.m.s. value] = [Peak value] x

Duty

Note

Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even

momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions which ensure

that the absolute maximum ratings are not exceeded.

CAPACITANCE (Ta = 25

C, V

= 0 V)

f=1 MHz

Unmeasured pins returned to 0 V.

PARAMETER

SYMBOL

TEST CONDITIONS

RATING

UNIT

0.3 to + 7.0

Except ports 4 & 5

0.3 to V

+ 0.3

Ports 4 & 5

0.3 to + 11

0.3 to V

+ 0.3

1 pin

All pins

1 pin

Peak value

R.m.s. value

Total for ports 0, 2, 3, 5

Peak value

100

R.m.s. value

Total for ports 4, 6, 7

Peak value

100

R.m.s. value

opt

40 to + 85

stg

65 to + 150

Supply voltage

Input voltage

Output voltage

Output current high

Output current low

Operating temperature

Storage temperature

TYP.

MAX.

UNIT

MIN.

PARAMETER

Input capacitance

Output capacitance

I/O capacitance

TEST CONDITIONS

SYMBOL

OUT

PD75B316B

MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (T

= 40 to +85

C, V

= 2.0 to 6.0 V)

RESONATOR

Ceramic

resonator*3

Crystal*3

External

clock

UNIT

MHz

1. The oscillation frequency and X1 input frequency are only indications of the oscillator characteristics. See

the AC characteristics for instruction execution times.

2. The oscillation stabilization time is the time required for oscillation to stabilize after V

reaches the MIN.

value of the oscillation voltage range, or the STOP mode is released.

3. When the oscillation frequency is 4.19 MHz < f

<= 5.0MHz, PCC = 0011 should not be selected as the

instruction execution time. If PCC = 0011 is selected, one machine cycle will be less than 0.95 us, and the MIN.

value of 0.95 us in the specification will not be achieved.

Note

When the main system clock oscillator is used, the following should be noted concerning wiring in the area

in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc.

· The wiring should be kept as short as possible.

· No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current.

· The oscillator capacitor grounding point should always be at the same potential as V

. Do not connect

to a ground pattern carrying a high current.

· A signal should not be taken from the oscillator.

MAX.

5.0*3

500

TYP.

4.19

MIN.

1.0

100

TEST CONDITIONS

After V

has reached MIN.

of oscillation voltage range.

=4.5 to 6.0 V

PARAMETER

Oscillation frequency

)*1

Oscillation stabilization

time*2

Oscillation frequency

)*1

Oscillation stabilization

time*2

X1 input frequency

)*1

X1 input high-/low-level

width (t

, t

)

RECOMENDED CONSTANT

PD74HCU04

PD75P316B

SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = 40 to +85

C, V

= 2.0 to 6.0 V)

RECOMENDED CONSTANT

UNIT

kHz

RESONATOR

Crystal

resonator

External

clock

This is the time required for oscillation to stabilize after V

reaches the MIN. value of the oscillation voltage

range.

Note

When the subsystem clock oscillator is used, the following should be noted concerning wiring in the area

in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc.

· The wiring should be kept as short as possible.

· No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current.

· The oscillator capacitor grounding point should always be at the same potential as V

. Do not connect

to a ground pattern carrying a high current.

· A signal should not be taken from the oscillator.

The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current,

and is more prone to misoperation due to noise than the main system clock oscillator. Particular care is

therefore required with the wiring method when the subsystem clock is used.

MAX.

100

TYP.

1.0

32.768

MIN.

TEST CONDITIONS

=4.5 to 6.0 V

PARAMETER

Oscillation frequency

)

Oscillation stabilization

time*

XT1 input frequency

)

XT1 input high-/low-

level width (t

XTH

, t

XTL

)

XT2

XT1

XT2

XT1

Open

PD75B316B

1.0

Input voltage
high

Input voltage
low

OH1

OH2

2.0

Output voltage
high

0.4

1.0

LOH2

OUT

= 10 V

LIH3

= 10 V

OL2

SB0, 1

0.2 V

(1) V

=2.7 to 6.0 V

DC CHARACTERISTICS (Ta = 40 to +85

C, V

= 2.7 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

IH1

Ports 2 and 3

0.7 V

IH2

Ports 0, 1, 6, 7 and RESET

0.8 V

IH3

Ports 4 and 5

0.7 V

IH4

X1, X2, XT1

0.5

IL1

Ports 2, 3, 4, 5

0.3 V

IL2

Ports 0, 1, 6, 7 and RESET

0.2 V

IL3

X1, X2, XT1

0.4

= 4.5 to 6.0 V

Ports 0, 2, 3, 6, 7,

= 1 mA

and BIAS

= -100

0.5

= 4.5 to 6.0 V

BP0 to BP7

= 100

(with 2 I

outputs)

= 30

1.0

Ports 3, 4, 5
V

= 4.5 to 6.0 V

0.7

2.0

= 15 mA

Ports
0, 2, 3, 4, 5, 6, 7

= 4.5 to 6.0 V

OL1

= 1.6 mA

= 400

0.5

Opendrain
pull-up resistor

1 k

= 4.5 to 6.0 V

BP0 to BP7

= 100

(with 2 I

outputs)

= 50

1.0

L1H1

Other than below

= V

LIH2

X1, X2, XT1

Ports 4 and 5

Input leakage

LIL1

Other than below

current low

= 0 V

LIL2

X1, X2, XT1

Output leakage

LOH1

OUT

= V

Other than below

current high

Ports 4 and 5

Output leakage
current low

Output voltage
low

Input leakage
current high

LOL

OUT

= 0 V

PD75P316B

DC CHARACTERISTICS (Ta = 40 to +85

C, V

= 2.7 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Ports 0, 1, 2, 3, 6, 7

= 5.0 V

10%

(Except P00)
V

= 0 V

= 3.0 V

10%

200

LCD drive voltage

LCD

2.0

LCD output voltage
deviation*1

ODC

0.2

(common)

LCD output voltage
deviation

ODS

0.2

(segment)

= 5 V

10%*4

4.0

DDI

4.19 MHz*3

= 3 V

10%*5

0.5

1.5

crystal oscillation
C1 = C2 = 22 pF

HALT

= 5 V

10%

DD2

mode

= 3 V

10%

300

900

DD3

= 3 V

10%

32 kHz*6
crystal oscillation

HALT

= 3 V

10%

mode

= 5 V

10%

DD5

0.5

Ta = 25

0.5

* 1.

The voltage deviation is the difference between the output voltage and the ideal value of the common output

LCDn

; n = 0, 1, 2).

Excluding the current flowing in the internal pull-up resistor.

Including the case where the subsystem clock is oscillated.

When the processor clock control register (PCC) is set to 0011 for operation in high-speed mode.

When PCC is set to 0000 for operation in low-speed mode.

When the system clock control register (SCC) is set to 1001, main system clock oscillation is stopped, and

the device is operated on the subsystem clock.

Internal pull-up
resistor

LCD0

= V

LCD

LCD1

= V

LCD

2/3

LCD2

= V

LCD

1/3

2.7 V

LCD

DD4

3 V

10%

XT1 = 0 V
STOP mode

Supply current*2

PD75B316B

TIH

TIL

INTH

INTL

vs V

(Operating on Main System Clock)

Cycle Time t

[

Supply Voltage V

[V]

0.5

Guaranteed

Operation Range

AC CHARACTERISTICS (Ta = 40 to +85

C, V

= 2.7 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Operating on main

= 4.5 to 6.0 V

0.95

system clock

3.8

Operating on
subsystem clock

TI0 input

= 4.5 to 6.0 V

MHz

frequency

275

kHz

TI0 input high-/low-

= 4.5 to 6.0 V

0.48

level width

1.8

INT0

INT1, 2, 4

KR0 to KR7

RESET low-level

RSL

width

114

122

125

Interrupt input
high-/low-level
width

* 1.

The CPU clock (

) cycle time (minimum instruc-

tion execution time) is determined by the oscil-

lation frequency of the connected resonator, the

system clock control register (SCC), and the

processor control register (PCC).

The graph on the right shows the characteristic

of the cycle time t

against the supply current

in the case of main system clock operation.

or 128/f

depending on the setting of the

interrupt mode register (IM0).

CPU clock
cycle time*1
(minimum
instruction
execution time
= 1 machine cycle)

PD75P316B

SIK2

100

SERIAL TRANSFER OPERATIONS

2-Wired and 3-Wired Serial I/O Modes (SCK ... Internal clock output): (Ta = 40 to +85

C, V

= 2.7 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

= 4.5 to 6.0 V

1600

SCK cycle time

KCY1

3800

SCK high-/low-level

= 4.5 to 6.0 V

KCY1

/2-50

width

KCY1

/2-150

SI setup time
(to SCK

)

SI hold time
(from SCK

)

SO output

= 4.5 to 6.0 V

250

delay time

KSO1

from SCK

1000

2-Wired and 3-Wired Serial I/O Modes (SCK ... External clock input): (Ta = -40 to +85

C, V

= 2.7 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

SCK cycle time

= 4.5 to 6.0 V

800

KCY2

3200

SCK high-/low-level

= 4.5 to 6.0 V

400

width

1600

SI setup time
(to SCK

)

SI hold time
(from SCK

)

SO output

= 4.5 to 6.0 V

300

delay time

KSO2

from SCK

1000

and C

are the SO output line load resistance and load capacitance.

SIK1

150

KSI1

400

KL1

KH1

KSI2

400

KL2

KH2

= 1 k

= 100 pF

= 1 k

= 100 pF

PD75B316B

SBI Mode (SCK ... Internal clock output (Master)): (Ta = 40 to +85

C, V

= 2.7 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

SCK cycle time

= 4.5 to 6.0 V

1600

KCY3

3800

SCK high-/low-level

= 4.5 to 6.0 V

KCY3

/2-50

width

KCY3

/2-150

SB0, 1 setup time
(to SCK

)

SB0, 1 hold time
(from SCK

)

SB0, 1 output

= 4.5 to 6.0 V

250

delay time from

KSO3

SCK

1000

SB0, 1

from SCK

KSB

KCY3

SCK from SB0, 1

SBK

KCY3

SBL

KCY3

SBH

KCY3

SBI Mode (SCK ... External clock input (Slave)): (Ta = 40 to +85

C, V

= 2.7 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

SCK cycle time

= 4.5 to 6.0 V

800

KCY4

3200

SCK high-/low-level

= 4.5 to 6.0 V

400

width

1600

SB0, 1 setup time
(to SCK

)

SB0, 1 hold time
(from SCK

)

SB0, 1 output

= 4.5 to 6.0 V

300

delay time from

KSO4

SCK

1000

SB0, 1

from SCK

KSB

KCY4

SCK

from SB0, 1

SBK

KCY4

SBL

KCY4

SBH

KCY4

and C

are the SB0, 1 output line load resistance and load capacitance.

SIK3

150

KSI3

KCY3

KL3

KH3

SB0, 1 low-level
width

SB0, 1 high-level
width

KSI4

KCY4

SIK4

100

KL4

KH4

= 1 k

= 100 pF

= 1 k

= 100 pF

SB0, 1 high-level
width

SB0, 1 low-level
width

PD75P316B

(2) V

=2.7 to 6.0 V

DC CHARACTERISTICS (Ta = 40 to +85

C, V

= 2.0 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

IH1

Ports 2 and 3

0.8 V

IH2

Ports 0, 1, 6, 7 and RESET

0.8 V

IH3

Ports 4 and 5

0.8V

IH4

X1, X2, XT1

0.3

IL1

Ports 2, 3, 4, 5

0.2 V

IL2

Ports 0, 1, 6, 7 and RESET

0.2 V

IL3

X1, X2, XT1

0.25

Ports 0, 2, 3, 6, 7
and BIAS

BP0 to BP7 (with
2 I

outputs)

Ports 0, 2, 3, 4, 5
6, 7

OL1

Opendrain,
pull-up resistor

1 k

BP0 to BP7
(with 2 I

outputs)

LIH1

Other than below

= V

LIH2

X1, X2, XT1

Ports 4 and 5

Input leakage

LIL1

Other than below

current low

= 0 V

LIL2

X1, X2, XT1

Output leakage

LOH1

OUT

= V

Other than below

current high

LOH2

OUT

= 10 V

Ports 4 and 5

Output leadage

LOL

OUT

= 0 V

current low

Ports 0, 1, 2, 3, 6, 7

(Except P00)

= 2.5 V

10%

600

= 0 V

LCD drive voltage

LCD

2.0

Input voltage
high

Input voltage
low

OH2

= 10

0.4

OH1

= 100

0.5

Output voltage
high

= 400

0.5

SB0, 1

0.2 V

Output voltage
low

OL2

= 10

0.4

Input leakage
current high

LIH3

= 10 V

Internal pull-up
resistor

PD75B316B

DC CHARACTERISTICS (Ta = 40 to +85

C, V

= 2.0 to 6.0 V)

LCDO

= V

LCD

LCD1

= V

LCD

2/3

LCD2

= V

LCD

1/3

2.0 V

LCD

4.19 MHz*3
crystal oscillation
C1 = C2 = 22 pF
low-speed mode

32 kHz*5
crystal oscillation

XT1 = 0 V
STOP mode

= 2.5 V

10%

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

LCD output voltage
deviation *1

ODC

0.2

(common)

LCD output
voltage deviation

ODS

0.2

(segment)

= 3 V

10%*4

0.5

1.5

DDI

= 2.5 V

10%*4

0.4

1.2

HALT

= 3 V

10%

300

900

DD2

mode

= 2.5 V

10%

200

600

= 3 V

10%

DD3

Supply current*2

= 2.5 V

10%

HALT

= 3 V

10%

DD4

mode

= 2.5 V

10%

0.5

= 3 V

10%

Ta = 25

0.5

DD5

0.4

Ta = 25

0.4

* 1.

The voltage deviation is the difference between the output voltage and the ideal value of the common

output (V

LCDn

; n = 0, 1, 2).

Excluding the current flowing in the internal pull-up resistor.

Including the case where the subsystem clock is oscillated.

When PCC is set to 0000 for operation in low-speed mode.

When the system clock control register (SCC) is set to 1001, main system clock oscillation is stopped, and

the device is operated on the subsystem clock.

PD75P316B

1.8

3.4

275

kHz

INTH

INTL

* 1.

The CPU clock (

) cycle time (minimum instruc-

tion execution time) is determined by the oscil-

lation frequency of the connected resonator,

the system clock control register (SCC), and the

processor clock control register (PCC).

The graph on the right shows the characteristic

of the cycle time t

against the supply current

in the case of main system clock operation.

or 128/f

depending on the setting of the

interrupt mode register (IMO).

vs V

(Operating on Main System Clock)

Cycle Time t

[

Supply Voltage V

[V]

0.5

Guaranteed

Operation Range

114

122

125

AC CHARACTERISTICS (Ta = 40 to +85

C, V

= 2.0 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

= 2.7 to 6.0 V

3.8

Operating on main

= 2.0 to 6.0 V

system clock

Ta = 40 to + 60

= 2.2 to 6.0 V

Operating on
subsystem clock

TI0 input
frequency

TI0 input high-/low-

TIH

level width

TIL

INT0

INT1, 2, 4

KR0 to KR7

RESET low-level

RSL

width

Interrupt input
high-/low-level
width

CPU clock
cycle time
(minimum instruc-
tion execution time
= 1 machine
cycle)*1

PD75B316B

SERIAL TRANSFER OPERATIONS

2-Wired and 3-Wired Serial I/O Mode (SCK ... Internal clock output): (Ta = 40 to +85

C, V

= 2.0 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

SCK cycle time

= 4.5 to 6.0 V

1600

KCY1

3800

SCK high-/low-

= 4.5 to 6.0 V

KCY1

/2-50

level width

KCY1

/2-150

SI setup time
(to SCK

)

SI hold time
(from SCK

)

SO output

= 4.5 to 6.0 V

250

delay time

KSO1

from SCK

1000

2-Wired and 3-Wired Serial I/O Mode (SCK ... External clock input): (Ta = 40 to +85

C, V

= 2.0 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

SCK cycle time

= 4.5 to 6.0 V

800

KCY2

3200

SCK high-/low-

= 4.5 to 6.0 V

400

level width

1600

SI setup time
(to SCK

)

SI hold time
(from SCK

)

SO output

= 4.5 to 6.0 V

300

delay time

KSO2

from SCK

1000

and C

are the SO output line load resistance and load capacitance.

KSI2

400

SIK2

100

KL1

KH1

KSI1

400

SIK1

250

= 1 k

= 100 pF*

KL2

KH2

= 1 k

= 100 pF*

PD75P316B

SIK4

100

KSI4

KCY4

KL4

KH4

= 1 k

= 100 pF*

SBI Mode (SCK ... Internal clock output (Master)): (Ta = 40 to +85

C, V

= 2.0 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

SCK cycle time

= 4.5 to 6.0 V

1600

KCY3

3800

SCK high-/low-

= 4.5 to 6.0 V

KCY3

/2-50

level width

KCY3

/2-150

SB0, 1 setup
time (to SCK

)

SB0, 1 hold
time (from SCK

)

SB0, 1 output

= 4.5 to 6.0 V

250

delay time

KSO3

from SCK

1000

SB0, 1

from SCK

KSB

KCY3

SCK from SB0, 1

SBK

KCY3

SBL

KCY3

SBH

KCY3

SBI Mode (SCK ... External clock input (Slave)): (Ta = 40 to +85

C, V

= 2.0 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

SCK cycle time

= 4.5 to 6.0 V

800

KCY4

3200

SCK high-/low-

= 4.5 to 6.0 V

400

level width

1600

SB0, 1 setup
time (to SCK

)

SB0, 1 hold
time (from SCK

)

SB0, 1

= 4.5 to 6.0 V

300

output delay

KSO4

time from SCK

1000

SB0, 1

from SCK

KSB

KCY4

SCK

from SB0, 1

SBK

KCY4

SBL

KCY4

SBH

KCY4

and C

are the SBO, 1 output line load resistance and load capacitance.

KSI3

KCY3

SIK3

250

KL3

KH3

= 1 k

= 100 pF*

SB0, 1 low-level
width

SB0, 1 high-level
width

SB0, 1 low-level
width

SB0, 1 high-level
width

PD75P316B

DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = 40 to +85

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Data retention supply voltage

DDDR

2.0

6.0

Data retention supply current*1

DDDR

= 2.0 V

0.3

Release signal setting time

SREL

Oscillation stabilization

Release by RESET

/fx

wait time*2

WAIT

Release by interrupt request

* 1.

Excluding current flowing in the internal pull-up resistor.

The oscillation stabilization time is the time during which the CPU operation is stopped to prevent unstable

operation when oscillation is started.

Depends on the basic interval timer mode register (BTM) setting ( see table below).

WAIT TIME

BTM3

BTM2

BTM1

BTM0

(Figure in ( ) is for fx = 4.19 MHz)

/fx (Approx. 250 ms)

/fx (Approx. 31.3 ms)

/fx (Approx. 7.82 ms)

/fx (Approx. 1.95 ms)

PD75P316B

DC PROGRAMMING CHARACTERISTICS (Ta = 25

C, V

= 6.0

0.25 V, V

= 12.5

0.3 V, V

= 0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

IH1

Except X1, X2

0.7 V

IH2

X1, X2

0.5

IL1

Except X1, X2

0.3 V

IL2

X1, X2

0.4

= V

= 1 mA

1.0

= 1.6 mA

0.4

supply

current

supply

MD0 = V

, MDI = V

current

Note

1. Ensure that V

does not exeed +13.5 V including overshoot.

2. V

must be applied before V

, and cut after V

Input voltage
high

Input voltage
low

Input leakage
current

Output voltage
high

Outputvoltage
low

PD75B316B

DC PROGRAMMING CHARACTERISTICS (Ta = 25

C, V

= 6.0

0.25 V, V

= 12.5

0.3 V, V

= 0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Address setup time*2 (to MD0

)

MD1 setup time (to MD0

)

M1S

OES

Data setup time (to MD0

)

Address hold time*2 (from MD0

)

Data hold time (from MD0

)

Data output float delay time from MD0

130

setup time (to MD3

)

VPS

setup time (to MD3

)

VDS

VCS

Initial program pulse width

0.95

1.0

1.05

Additional program pulse width

OPW

0.95

21.0

MD0 setup time (to MD1

)

MOS

CES

Data output delay time from MD0

MD0=MD1=V

MD1 hold time (from MD0

)

M1H

OEH

MD1 recovery time (from MD0

)

M1R

Program counter reset time

PCR

X1 input high-/low-level width

, t

0.125

X1 input frequency

4.19

MHz

Initial mode setting time

MD3 setup time (to MD1

)

M3S

MD3 hold time (from MD1

)

M3H

MD3 setup time (to MD0

)

M3SR

Program memory read

Data output delay time from address*2

DAD

ACC

Program memory read

Data output hold time from address*2

HAD

Program memory read

130

MD3 hold time (from MD0

)

M3HR

Program memory read

Data output float delay time from MD3

DFR

Program memory read

* 1.

Symbol of corresponding

PD27C256A

The internal address signal is incremented by 1 on the 4th rise of the X1 input, and is not connected to a pin.

M1H

M1R

PD75P316B

Program Memory Write Timing

VPS

VDS

M1R

M0S

PCR

M1S

M1H

M3S

M3H

OPW

Data Input

Data Output

Data Input

+ 1

P40 - P43
P50 - P53

MD0

MD1

MD2

MD3

Program Memory Read Timing

+ 1

MD0

MD1

MD2

MD3

VPS

M3SR

HAD

DAD

M3HR

DFR

PCR

VDS

Data Output

P40 - P43
P50 - P53

PD75P316B

PACKAGE INFORMATION

80 PIN PLASTIC QFP ( 14)

detail of lead end

5°±5°

S80GC-65-3B9-3

ITEM

MILLIMETERS

INCHES

17.2±0.4

14.0±0.2

0.8

0.30±0.10

0.13

14.0±0.2

0.677±0.016

0.031

0.005

0.026 (T.P.)

0.551

NOTE

0.10

0.15

1.6±0.2

0.65 (T.P.)

0.004

0.006

+0.004

0.003

Each lead centerline is located within 0.13
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

0.063±0.008

0.012

0.551

0.8±0.2

0.031

2.7

0.106

0.677±0.016

17.2±0.4

0.8

+0.009

0.008

0.1±0.1

0.004±0.004

3.0 MAX.

0.119 MAX.

+0.10

0.05

+0.009

0.008

+0.004

0.005

+0.009

0.008

PD75P316B

80 PIN PLASTIC TQFP (FINE PITCH) ( 12)

ITEM MILLIMETERS

INCHES

0.5 (T.P.)

0.10

0.004

0.020 (T.P.)

NOTE

Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.

14.0±0.2

0.551 +0.009

0.008

12.0±0.2

0.472 +0.009

0.008

12.0±0.2

0.472 +0.009

0.008

14.0±0.2

0.551 +0.009

0.008

1.25

0.049

0.22

0.009±0.002

P80GK-50-BE9-4

1.27 MAX.

0.050 MAX.

1.0±0.2

0.039 +0.009

0.008

0.5±0.2

0.020 +0.008

0.009

0.145

0.006±0.002

0.10

0.004

1.05

0.041

0.05±0.05

0.002±0.002

5°±5°

+0.05

0.04

+0.055

0.045

detail of lead end

PD75P316B

X80KW-65A-1

ITEM

MILLIMETERS

INCHES

14.0±0.2

13.6

3.6 MAX.

0.06

13.6

0.551±0.008

0.072

0.142 MAX.

0.003

0.024 (T.P.)

0.535

NOTE

0.825

0.65 (T.P.)

0.032

Each lead centerline is located within 0.06
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.

0.018

0.535

R 2.0

R 0.079

0.551±0.008

14.0±0.2

1.84

9.0

0.354

2.1

0.083

+0.004

0.005

0.10

0.004

0.45±0.10

0.039

+0.007

0.006

1.0±0.15

C 0.3

C 0.012

0.75±0.15

0.030

+0.006

0.007

80 PIN CERAMIC WQFN

PD75P316B

RECOMMENDED SOLDERING CONDITIONS

This product should be soldered and mounted under the conditions recommended in the table below.

For details of recommended soldering conditions for the surface mounting type, refer to the information

document "Surface Mount Technology Manual (IEI 1207)".

For soldering methods and conditions other than those recommended below, contact our salesman.

Table 7-1 Recommended Soldering Conditions

PD75P316BGC-3B9: 80-Pin Plastic QFP (

14 mm)

Soldering Method

Recommended Soldering Conditions

Recommended Condition Symbol

Package peak temperature: 230

Infrared reflow

Duration: 30 sec. max. (at 210

C or above);

IR35-00-1

Number of times: once;

Pin part heating

Pin part temperature: 300

C max.;

Duration: 3 sec. max. (per device side)

PD75P316BGK-

9: 80-Pin Plastic QFP (

12 mm)

Soldering Method

Recommended Soldering Conditions

Recommended Condition Symbol

Package peak temperature: 235

Duration: 30 sec. max. (at 210

C or above);

Infrared reflow

Number of times: once;

IR35-00-1

Timelimit: 7 days*(thereafter 10 hours prebaking required

at 125

Pin part heating

Pin part temperature: 300

C max.;

Duration: 3 sec. max. (per device side)

For the storage period after dry-pack decapsulation, storage conditions are max. 25

C, 65% RH.

Note

Use of more than one soldering method should be avoided (except in the case of pin part heating).

PD75P316B

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the

PD75P316B.

Hardware

Soft

ware

IE-75000-R*1

IE-75001-R

IE-7500-R-EM*2

EP-75308BGC-R

EV-9200GC-80

EP-75308BGK-R

EV-9500GK-80

PG-1500

PA-75P316BGC

PA-75P316BGK

IE control program

PG-1500 controller

RA75X relocatable assembler

75X series in-circuit emulator

Emulation board for IE-75000-R and IE-75001-R

Emulation probe for

PD75P316BGC.

Provided with EV-9200GC-80, 80-pin conversion socket.

PD75P316BGK emulation probe.

Provided with EV-9200GK-80, 80-pin conversion socket.

PROM programmer

PD75P316BGC programmer adapter. Connected with PG-1500.

PD75P316BGK programmer adapter. Connected with PG-1500.

Host Machine

PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3)

IBM PC/ATTM (PC DOSTM Ver.3.1)

1. Maintenance product

2. Not incorporated in the IE-75001-R.

3. The task swap function, which is provided with Ver.5.00/5.00A, is not available with this software.

PD75P316B

APPENDIX B. RELATED DOCUMENTS

Device Related Documents

Document Name

Document Number

User's Manual

IEM-5016

Instruction Application Table

IEM-994

Application Note

IEM-5035

IEM-5041

75X Series Selection Guide

IF-151

Development Tools Documents

Document Name

Document Number

IE-75000-R/IE-75001-R User's Manual

EEU-846

IE-75000-R-EM User's Manual

EEU-673

EP-75308BGC-R User's Manual

EEU-825

EP-75308BGK-R User's Manual

EEU-838

PG-1500 User's Manual

EEU-651

RA75X Assembler Package User's Manual

Operation

EEU-731

Language

EEU-730

PG-1500 Controller User's Manual

EEU-704

Other Documents

Document Name

Document Number

Package Manual

IEI-635

Surface Mount Technology Manual

IEI-1207

Quality Grande on NEC Semiconductor Device

IEI-1209

NEC Semiconductor Device Reliability & Quality Control

IEM-5068

Electrostatic Discharge(ESD) Test

MEM-539

Semiconductor Devices Quality Guarantee Guide

MEI-603

Microcomputer Related Products Guide Other Manufacturers Volume

MEI-604

The contents of the above related documents are subject to change without notice. The latest documents

should be used for design, etc.

Hardware

Soft

ware

[MEMO]

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this

document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from use of a device described herein or any other liability arising

from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights

or other intellectual property rights of NEC Corporation or others.

The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear

reactor control systems and life support systems. If customers intend to use NEC devices for above applications

or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact

our sales people in advance.

Application examples recommended by NEC Corporation

Standard :

Computer, Office equipment, Communication equipment, Test and Measurement equipment,

Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.

Special

Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,

Anticrime systems, etc.

M4 92.6

PD75P316B

Document Outline

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Document Outline

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